Antonio Calomarde
Antonio Calomarde
Verified email at upc.edu - Homepage
TitleCited byYear
Impact of FinFET and III–V/Ge technology on logic and memory cell behavior
E Amat, A Calomarde, CG Almudéver, N Aymerich, R Canal, A Rubio
IEEE Transactions on Device and Materials Reliability 14 (1), 344-350, 2013
122013
Feasibility of embedded DRAM cells on FinFET technology
E Amat, A Calomarde, F Moll, R Canal, A Rubio
IEEE Transactions on Computers 65 (4), 1068-1074, 2014
112014
All-digital simple clock synthesis through a glitch-free variable-length ring oscillator
J Pérez-Puigdemont, F Moll, A Calomarde
IEEE Transactions on Circuits and Systems II: Express Briefs 61 (2), 90-94, 2014
82014
A single event transient hardening circuit design technique based on strengthening
A Calomarde, E Amat, F Moll, A Rubio
2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013
72013
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
D Andrade, F Martorell, A Calomarde, F Moll, A Rubio
Microelectronics Journal 40 (6), 952-957, 2009
72009
Reliability study on technology trends beyond 20nm
E Amat, A Calomarde, A Rubio
Proceedings of the 20th International Conference Mixed Design of Integrated …, 2013
62013
Novel redundant logic design for noisy low voltage scenarios
L Garcia-Leyva, A Calomarde, F Moll, A Rubio
2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013
62013
SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET
A Calomarde, E Amat, F Moll, J Vigara, A Rubio
Microelectronics Reliability 54 (4), 738-745, 2014
52014
Variation tolerant self-adaptive clock generation architecture based on a ring oscillator
J Pérez-Puigdemont, A Calomarde, F Moll
2012 IEEE International SOC Conference, 387-392, 2012
52012
New redundant logic design concept for high noise and low voltage scenarios
L García-Leyva, D Andrade, S Gómez, A Calomarde, F Moll, A Rubio
Microelectronics journal 42 (12), 1359-1369, 2011
42011
A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits
D Andrade, A Calomarde, A Rubio
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 141-144, 2010
42010
Variability impact on on-chip memory data paths
E Amat, A Calomarde, R Canal, A Rubio
2014 5th European Workshop on CMOS Variability (VARI), 1-5, 2014
32014
All-digital self-adaptive PVTA variation aware clock generation system for DFS
J Pérez-Puigdemont, A Calomarde, F Moll
2014 5th European Workshop on CMOS Variability (VARI), 1-4, 2014
22014
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations
D Andrade, A Rubio, A Calomarde, SD Cotofana
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2585-2588, 2011
22011
Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits
L Garcia-Leyva, A Calomarde, F Moll, A Rubio
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 1101 …, 2010
22010
Fundamentos de electrónica
A Calomarde Palomino
Edicions UPC, 2002
12002
Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs
E Amat, A Calomarde, R Canal, A Rubio
Journal of Low Power Electronics 14 (2), 236-243, 2018
2018
Review on suitable eDRAM configurations for next nano-metric electronics era
E Amat, R Canal Corretger, A Calomarde Palomino, JA Rubio Sola
International journal of the Society of Materials Engineering for Resources …, 2018
2018
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
E Amat, A Calomarde, R Canal, A Rubio
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
2017
Active charge collection strategy for radiation environment at device level
A Calomarde, E Amat, A Rubio, F Moll, F Gamiz
2016 16th European Conference on Radiation and Its Effects on Components and …, 2016
2016
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Articles 1–20