| The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis W Wang, S Yang, S Bhardwaj, S Vrudhula, F Liu, Y Cao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (2), 173-183, 2009 | 362 | 2009 |
| Full chip leakage estimation considering power supply and temperature variations H Su, F Liu, A Devgan, E Acar, S Nassif Proceedings of the 2003 international symposium on Low power electronics and …, 2003 | 353 | 2003 |
| The impact of NBTI on the performance of combinational and sequential circuits W Wang, S Yang, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, Y Cao Proceedings of the 44th annual Design Automation Conference, 364-369, 2007 | 296 | 2007 |
| Model order-reduction of RC (L) interconnect including variational analysis Y Liu, LT Pileggi, AJ Strojwas Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 201-206, 1999 | 197 | 1999 |
| Impact of interconnect variations on the clock skew of a gigahertz microprocessor Y Liu, SR Nassif, LT Pileggi, AJ Strojwas Proceedings of the 37th Annual Design Automation Conference, 168-171, 2000 | 178 | 2000 |
| Rigorous extraction of process variations for 65-nm CMOS design W Zhao, F Liu, K Agarwal, D Acharyya, SR Nassif, KJ Nowka, Y Cao IEEE Transactions on Semiconductor Manufacturing 22 (1), 196-203, 2009 | 140 | 2009 |
| A test structure for characterizing local device mismatches K Agarwal, F Liu, C McDowell, S Nassif, K Nowka, M Palmer, D Acharyya, ... 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 67-68, 2006 | 140 | 2006 |
| A general framework for spatial correlation modeling in VLSI design F Liu Proceedings of the 44th annual Design Automation Conference, 817-822, 2007 | 130 | 2007 |
| Variational delay metrics for interconnect timing analysis K Agarwal, D Sylvester, D Blaauw, F Liu, S Nassif, S Vrudhula Proceedings of the 41st annual Design Automation Conference, 381-384, 2004 | 115 | 2004 |
| Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness Y Ye, F Liu, M Chen, S Nassif, Y Cao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (6), 987-996, 2010 | 113 | 2010 |
| Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals P Feldmann, F Liu IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 113 | 2004 |
| Modeling interconnect variability using efficient parametric model order reduction P Li, T Liu, X Li, LT Pileggi, SR Nassif Design, Automation and Test in Europe, 958-963, 2005 | 99 | 2005 |
| A delay metric for RC circuits based on the Weibull distribution F Liu, C Kashyap, CJ Alpert Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 97 | 2002 |
| Predicting variability in nanoscale lithography processes DG Drmanac, F Liu, LC Wang Proceedings of the 46th Annual Design Automation Conference, 545-550, 2009 | 77 | 2009 |
| Modeling and analysis of non-rectangular gate for post-lithography circuit simulation R Singhal, A Balijepalli, A Subramaniam, F Liu, S Nassif, Y Cao Proceedings of the 44th annual Design Automation Conference, 823-828, 2007 | 76 | 2007 |
| Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness Y Ye, F Liu, S Nassif, Y Cao Proceedings of the 45th annual Design Automation Conference, 900-905, 2008 | 74 | 2008 |
| Virtual probe: A statistical framework for low-cost silicon characterization of nanoscale integrated circuits W Zhang, X Li, F Liu, E Acar, RA Rutenbar, RD Blanton IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 72 | 2011 |
| Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees CV Kashyap, CJ Alpert, F Liu, A Devgan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 66 | 2004 |
| Applying microprocessor analysis methods to river network modelling F Liu, BR Hodges Environmental Modelling & Software 52, 234-252, 2014 | 60 | 2014 |
| A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits RM Rao, F Liu, JL Burns, RB Brown ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 59 | 2003 |
