Woogeun Rhee
Woogeun Rhee
Verified email at tsinghua.edu.cn
Cited by
Cited by
Design of high-performance CMOS charge pumps in phase-locked loops
W Rhee
1999 IEEE International Symposium on Circuits and Systems (ISCAS) 2, 545-548, 1999
A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order/spl Delta//spl Sigma/modulator
W Rhee, BS Song, A Ali
IEEE Journal of Solid-State Circuits 35 (10), 1453-1460, 2000
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
JF Bulzacchelli, M Meghelli, SV Rylov, W Rhee, AV Rylyakov, HA Ainspan, ...
IEEE Journal of Solid-State Circuits 41 (12), 2885-2900, 2006
A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-N synthesizer
R Magoon, A Molnar, J Zachan, G Hatcher, W Rhee
IEEE Journal of Solid-State Circuits 37 (12), 1710-1720, 2002
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
T Beukema, M Sorna, K Selander, S Zier, BL Ji, P Murfet, J Mason, ...
IEEE Journal of Solid-State Circuits 40 (12), 2633-2645, 2005
An ultra-compact differentially tuned 6-GHz CMOS LC-VCO with dynamic common-mode feedback
B Soltanian, H Ainspan, W Rhee, D Friedman, PR Kinget
IEEE journal of solid-state circuits 42 (8), 1635-1641, 2007
Phase interpolated fractional-N frequency synthesizer with on-chip tuning
W Rhee
US Patent 6,064,272, 2000
A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
M Meghelli, S Rylov, J Bulzacchelli, W Rhee, A Rylyakov, H Ainspan, ...
2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006
A 13.3 mW 500 Mb/s IR-UWB transceiver with link margin enhancement technique for meter-range communications
S Geng, D Liu, Y Li, H Zhuo, W Rhee, Z Wang
IEEE Journal of Solid-State Circuits 50 (3), 669-678, 2015
Quantitative analysis of mitotic Olig2 cells in adult human brain and gliomas: implications for glioma histogenesis and biology
W Rhee, S Ray, H Yokoo, ME Hoane, CC Lee, AM Mikheev, PJ Horner, ...
Glia 57 (5), 510-523, 2009
Source-switched or gate-switched charge pump having cascoded output
W Rhee, M Conta
US Patent 6,160,432, 2000
A dual-channel compass/GPS/GLONASS/Galileo reconfigurable GNSS receiver in 65 nm CMOS with on-chip I/Q calibration
N Qi, Y Xu, B Chi, X Yu, X Zhang, N Xu, P Chiang, W Rhee, Z Wang
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1720-1732, 2012
An FIR-Embedded Noise Filtering Method for Fractional-N PLL Clock Generators
X Yu, Y Sun, W Rhee, Z Wang
IEEE journal of solid-state circuits 44 (9), 2426-2436, 2009
An on-chip phase compensation technique in fractional-N frequency synthesis
W Rhee, A Ali
1999 IEEE International Symposium on Circuits and Systems (ISCAS) 3, 363-366, 1999
A 6.4 Gb/s CMOS SerDes core with feedforward and decision-feedback equalization
M Sorna, T Beukerna, K Selander, S Zier, B Ji, P Murfet, J Mason, W Rhee, ...
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005
A Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications
X Yu, Y Sun, W Rhee, HK Ahn, BH Park, Z Wang
IEEE journal of solid-state circuits 44 (8), 2193-2201, 2009
Semidigital delay-locked loop using an analog-based finite state machine
W Rhee, SV Rylov, D Friedman
US Patent 6,927,611, 2005
Blockage effect correction for a scaled wind turbine rotor by using wind tunnel test data
J Ryi, W Rhee, UC Hwang, JS Choi
Renewable Energy 79, 227-235, 2015
The innovative green technology for refrigerators development of innovative linear compressor
H Lee, S Ki, S Jung, W Rhee
Phase/frequency detector with time-delayed inputs in a charge pump based phase locked loop and a method for enhancing the phase locked loop gain
W Rhee, A Ali
US Patent 6,147,561, 2000
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