| An experimental study of n-detect scan ATPG patterns on a processor S Venkataraman, S Sivaraj, E Amyeen, S Lee, A Ojha, R Guo 22nd IEEE VLSI Test Symposium, 2004. Proceedings., 23-28, 2004 | 87 | 2004 |
| Evaluation of the quality of N-detect scan ATPG patterns on a processor ME Amyeen, S Venkataraman, A Ojha, S Lee 2004 International Conferce on Test, 669-678, 2004 | 77 | 2004 |
| Improving precision using mixed-level fault diagnosis ME Amyeen, D Nayak, S Venkataraman 2006 IEEE International Test Conference, 1-10, 2006 | 73 | 2006 |
| Evaluation of test metrics: Stuck-at, bridge coverage estimate and gate exhaustive R Guo, S Mitra, E Amyeen, J Lee, S Sivaraj, S Venkataraman 24th IEEE VLSI Test Symposium, 6 pp.-71, 2006 | 50 | 2006 |
| Fault equivalence identification using redundancy information and static and dynamic extraction ME Amyeen, WK Fuchs, I Pomeranz, V Boppana Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 124-130, 2001 | 47 | 2001 |
| Testing for systematic defects based on DFM guidelines D Kim, ME Amyeen, S Venkataraman, I Pomeranz, S Basumallick, ... 2007 IEEE International Test Conference, 1-10, 2007 | 33 | 2007 |
| Fault equivalence identification in combinational circuits using implication and evaluation techniques ME Amyeen, WK Fuchs, I Pomeranz, V Boppana IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 27 | 2003 |
| Defect diagnosis based on pattern-dependent stuck-at faults I Pomeranz, S Venkataraman, SM Reddy, E Amyeen 17th International Conference on VLSI Design. Proceedings., 475-480, 2004 | 25 | 2004 |
| Implication and evaluation techniques for proving fault equivalence ME Amyeen, WK Fuchs, I Pomeranz, V Boppana Proceedings 17th IEEE VLSI Test Symposium (Cat. No. PR00146), 201-207, 1999 | 21 | 1999 |
| Diagnostic resolution improvement through learning-guided physical failure analysis C Lim, Y Xue, X Li, RD Blanton, ME Amyeen 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 20 | 2016 |
| Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests N Wang, I Pomeranz, B Benware, E Amyeen, S Venkataraman IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2018 | 18 | 2018 |
| Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm S Bodhe, ME Amyeen, C Galendez, H Mooers, I Pomeranz, ... 2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016 | 18 | 2016 |
| Dominance based analysis for large volume production fail diagnosis B Seshadri, I Pomeranz, S Venkataraman, ME Amyeen, SM Reddy 24th IEEE VLSI Test Symposium, 6 pp.-399, 2006 | 18 | 2006 |
| Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation X Yu, ME Amyeen, S Venkataraman, R Guo, I Pomeranz Proceedings. 21st VLSI Test Symposium, 2003., 351-356, 2003 | 18 | 2003 |
| 3 is a more promising algorithmic parameter than 2 M Kaykobad, MM Islam, ME Amyeen, MM Murshed Computers & Mathematics with Applications 36 (6), 19-24, 1998 | 16 | 1998 |
| Defect diagnosis based on DFM guidelines D Kim, I Pomeranz, ME Amyeen, S Venkataraman 2010 28th VLSI Test Symposium (VTS), 206-211, 2010 | 14 | 2010 |
| Logic BIST silicon debug and volume diagnosis methodology ME Amyeen, A Jayalakshmi, S Venkataraman, SV Pathy, EC Tan 2011 IEEE International Test Conference, 1-10, 2011 | 13 | 2011 |
| Microprocessor system failures debug and fault isolation methodology ME Amyeen, S Venkataraman, MW Mak 2009 International Test Conference, 1-10, 2009 | 13 | 2009 |
| Diagnostic Fail Data Minimization Using an-Cover Algorithm S Bodhe, ME Amyeen, I Pomeranz, S Venkataraman IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (3 …, 2015 | 12 | 2015 |
| Using scan-dump values to improve functional-diagnosis methodology VC Vimjam, ME Amyeen, R Guo, S Venkataraman, M Hsiao, K Yang 25th IEEE VLSI Test Symposium (VTS'07), 231-238, 2007 | 12 | 2007 |
Irith PomeranzPurdue UniversityVerified email at ecn.purdue.edu
