Per Stenström
Per Stenström
Verified email at chalmers.se
Title
Cited by
Cited by
Year
The worst-case execution-time problem—overview of methods and survey of tools
R Wilhelm, J Engblom, A Ermedahl, N Holsti, S Thesing, D Whalley, ...
ACM Transactions on Embedded Computing Systems (TECS) 7 (3), 1-53, 2008
20712008
A survey of cache coherence schemes for multiprocessors
P Stenstrom
Computer 23 (6), 12-24, 1990
5371990
Timing anomalies in dynamically scheduled microprocessors
T Lundqvist, P Stenstrom
Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No. 99CB37054), 12-21, 1999
4451999
An adaptive cache coherence protocol optimized for migratory sharing
P Stenström, M Brorsson, L Sandberg
ACM SIGARCH Computer Architecture News 21 (2), 109-118, 1993
2271993
Comparative performance evaluation of cache-coherent NUMA and COMA architectures
P Stenström, T Joe, A Gupta
Proceedings of the 19th annual international symposium on Computer …, 1992
2221992
Sequential hardware prefetching in shared-memory multiprocessors
F Dahlgren, M Dubois, P Stenstrom
IEEE Transactions on Parallel and Distributed Systems 6 (7), 733-746, 1995
2101995
An integrated path and timing analysis method based on cycle-level symbolic execution
T Lundqvist, P Stenström
Real-Time Systems 17 (2-3), 183-207, 1999
2091999
SimICS/Sun4m: A Virtual Workstation.
PS Magnusson, F Larsson, A Moestedt, B Werner, J Nilsson, P Stenström, ...
Usenix Annual Technical Conference, 119-130, 1998
2081998
Fixed and adaptive sequential prefetching in shared memory multiprocessors
F Dahlgren, M Dubois, P Stenstrom
1993 International Conference on Parallel Processing-ICPP'93 1, 56-63, 1993
2011993
A robust main-memory compression scheme
M Ekman, P Stenstrom
32nd International Symposium on Computer Architecture (ISCA'05), 74-85, 2005
2002005
An adaptive shared/private nuca cache partitioning scheme for chip multiprocessors
H Dybdahl, P Stenstrom
2007 IEEE 13th International Symposium on High Performance Computer …, 2007
1642007
A prefetching technique for irregular accesses to linked data structures
M Karlsson, F Dahlgren, P Stenstrom
Proceedings Sixth International Symposium on High-Performance Computer …, 2000
1442000
The detection and elimination of useless misses in multiprocessors
M Dubois, J Skeppstedt, L Ricciulli, K Ramamurthy, P Stenström
ACM SIGARCH Computer Architecture News 21 (2), 88-97, 1993
1411993
Recency-based TLB preloading
A Saulsbury, F Dahlgren, P Stenström
Proceedings of the 27th annual international symposium on Computer …, 2000
1392000
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors
M Ekman, F Dahgren, P Stenstrom
Proceedings of the international symposium on Low power electronics and …, 2002
1142002
The cachemire test bench-a flexible and effective approach for simulation of multiprocessors
M Brorsson, F Dahlgren, H Nilsson, P Stenström
Annual Simulation Symposium 26, 41-41, 1993
1121993
Integrating path and timing analysis using instruction-level simulation techniques
T Lundqvist, P Stenström
Languages, Compilers, and Tools for Embedded Systems, 1-15, 1998
1041998
Evaluation of hardware-based stride and sequential prefetching in shared-memory multiprocessors
F Dahlgren, P Stenstrom
IEEE Transactions on Parallel and Distributed Systems 7 (4), 385-398, 1996
941996
SC2: a statistical compression cache scheme
A Arelakis, P Stenstrom
Proceeding of the 41st annual international symposium on Computer …, 2014
902014
An all-software thread-level data dependence speculation system for multiprocessors
P Rundberg, P Stenström
Journal of Instruction-Level Parallelism 3 (1), 2002, 2001
852001
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