Cu interconnect limitations and opportunities for SWNT interconnects at the end of the roadmap A Ceyhan, A Naeemi
IEEE Transactions on Electron Devices 60 (1), 374-382, 2012
105 2012 Impact of size effects in local interconnects for future technology nodes: A study based on full-chip layouts A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi
IEEE International Interconnect Technology Conference, 345-348, 2014
30 2014 Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node C Pan, P Raghavan, A Ceyhan, F Catthoor, Z Tokei, A Naeemi
IEEE Transactions on Electron Devices 62 (5), 1530-1536, 2015
27 2015 Adapting interconnect technology to multigate transistors for optimum performance D Prasad, A Ceyhan, C Pan, A Naeemi
IEEE Transactions on Electron Devices 62 (12), 3938-3944, 2015
22 2015 BEOL scaling limits and next generation technology prospects A Naeemi, A Ceyhan, V Kumar, C Pan, RM Iraei, S Rakheja
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
18 2014 Evaluating Chip-Level Impact of Cu/Low- A Ceyhan, M Jung, S Panth, SK Lim, A Naeemi
IEEE Transactions on Electron Devices 62 (3), 940-946, 2015
16 2015 Machine learning-enhanced multi-dimensional co-optimization of sub-10nm technology node options A Ceyhan, J Quijas, S Jain, HY Liu, WE Gifford, S Chakravarty
2019 IEEE International Electron Devices Meeting (IEDM), 36.6. 1-36.6. 4, 2019
14 2019 Cu/Low- A Ceyhan, A Naeemi
IEEE transactions on electron devices 60 (12), 4041-4047, 2013
14 2013 Impact of conventional and emerging interconnects on the circuit performance of various Post-CMOS devices A Ceyhan, A Naeemi
International Symposium on Quality Electronic Design (ISQED), 203-209, 2013
13 2013 Multilevel interconnect networks for the end of the roadmap: Conventional cu/low-k and emerging carbon based interconnects A Ceyhan, A Naeemi
2011 IEEE International Interconnect Technology Conference, 1-3, 2011
6 2011 Interconnects for future technology generations-conventional CMOS with copper/low-k and beyond A Ceyhan
Georgia Intitute of Technology, 2014
5 2014 System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs C Pan, A Ceyhan, A Naeemi
International Symposium on Quality Electronic Design (ISQED), 196-202, 2013
4 2013 Performance modeling for emerging interconnect technologies in CMOS and beyond-CMOS circuits SC Chang, A Ceyhan, V Kumar, A Naeemi
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
3 2014 Overview of the interconnect problem A Ceyhan, A Naeemi
Carbon Nanotubes for Interconnects: Process, Design and Applications, 3-36, 2017
2 2017 Interconnect issues: history and future prospects, part 2 A Ceyhan, A Naeemi
Future fab Intl., A thought leadership project from MazikMedia, Inc, 2013
2 2013 System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors A Ceyhan, A Naeemi
2012 IEEE International Conference on IC Design & Technology, 1-4, 2012
2 2012 15 Interconnect considerations S Rakheja, A Ceyhan, A Naeemi
CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, 381, 2015
1 2015 Novel IR/EM-Aware Power Grid Design and Analysis Methodologies for Optimal PPA at Sub-10nm Technology Nodes G Miller, S Jain, S Kelgeri, P Ranganathan, A Ceyhan
2021 IEEE International Interconnect Technology Conference (IITC), 1-3, 2021
2021 INTERCONNECTS FOR FUTURE TECHNOLOGY GENERATIONS—CONVENTIONAL CMOS WITH COPPER/LOW–κ AND BEYOND A Ceyhan
Georgia Institute of Technology, 2014
2014 Silicon and Column IV Semiconductors Devices D Prasad, A Ceyhan, C Pan, A Naeemi, P Zheng, D Connelly, F Ding, ...
