Andres otero
Andres otero
Universidad Politécnica de Madrid- Centro de Electrónica Industrial
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Using SRAM based FPGAs for power-aware high performance wireless sensor networks
J Valverde, A Otero, M Lopez, J Portilla, E de la Torre, T Riesgo
Sensors 12 (3), 2667-2692, 2012
582012
Adaptable security in wireless sensor networks by using reconfigurable ECC hardware coprocessors
J Portilla, A Otero, E de la Torre, T Riesgo, O Stecklina, S Peter, ...
International Journal of Distributed Sensor Networks 2010, 2010
562010
Self-reconfigurable evolvable hardware system for adaptive image processing
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
IEEE transactions on computers 62 (8), 1481-1493, 2013
552013
Fault tolerance analysis and self-healing strategy of autonomous, evolvable hardware systems
R Salvador, A Otero, J Mora, E de la Torre, L Sekanina, T Riesgo
Reconfigurable Computing and FPGAs (ReConFig), 2011 International Conference …, 2011
392011
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems
A Otero, E de la Torre, T Riesgo
2012 International Conference on Reconfigurable Computing and FPGAs, 1-8, 2012
382012
Fpga-based high-performance embedded systems for adaptive edge computing in cyber-physical systems: The artico3 framework
A Rodríguez, J Valverde, J Portilla, A Otero, T Riesgo, E De la Torre
Sensors 18 (6), 1877, 2018
342018
Automatic generation of identical routing pairs for FPGA implemented DPL logic
W He, A Otero, E de la Torre, T Riesgo
2012 International Conference on Reconfigurable Computing and FPGAs, 1-6, 2012
302012
A Modular Peripheral to Support Self-Reconfiguration in SoCs
A Otero, Á Morales-Cas, J Portilla, E de la Torre, T Riesgo
Digital System Design: Architectures, Methods and Tools (DSD), 2010 13th …, 2010
252010
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems
A Otero, R Salvador, J Mora, E de la Torre, T Riesgo, L Sekanina
Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on, 336-343, 2011
242011
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on, 184-191, 2011
182011
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration
R Salvador, A Otero, J Mora, E de la Torre, T Riesgo, L Sekanina
Field Programmable Logic and Applications (FPL), 2012 22nd International …, 2012
162012
On the automatic integration of hardware accelerators into FPGA-based embedded systems
C Pilato, A Cazzaniga, G Durelli, A Otero, D Sciuto, MD Santambrogio
22nd International Conference on Field Programmable Logic and Applications …, 2012
142012
A novel FPGA-based evolvable hardware system based on multiple processing arrays
Á Gallego, J Mora, A Otero, R Salvador, E de la Torre, T Riesgo
2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013
132013
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs
J Mora, A Otero, E de la Torre, T Riesgo
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
122015
A scalable evolvable hardware processing array
A Gallego, J Mora, A Otero, E de la Torre, T Riesgo
2013 International Conference on Reconfigurable Computing and FPGAs …, 2013
112013
Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems
A Pérez, L Suriano, A Otero, E de la Torre
2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 40-47, 2017
102017
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic
W He, A Otero, E de la Torre, T Riesgo
Microprocessors and Microsystems 38 (8), 899-910, 2014
102014
Generic systolic array for run-time scalable cores
A Otero, YE Krasteva, E de la Torre, T Riesgo
International Symposium on Applied Reconfigurable Computing, 4-16, 2010
102010
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems
J Valverde, A Rodríguez, J Camarero, A Otero, J Portilla, E de la Torre, ...
2014 24th International Conference on Field Programmable Logic and …, 2014
82014
Run-time Scalable Architecture for Deblocking Filtering in H. 264/AVC-SVC Video Codecs
A Otero, E De La Torre, T Riesgo, T Cervero, S López, G Callicó, ...
Field Programmable Logic and Applications (FPL), 2011 International …, 2011
82011
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Artículos 1–20