Gaurang R. Upasani

Cited by

	All	Since 2019
Citations	78	37
h-index	5	4
i10-index	4	1

20092010201120122013201420152016201720182019202020212022202320241 2 2 4 7 15 4 6 2 3 9 10 12 1

Public access

View all

2 articles

4 articles

available

not available

Based on funding mandates

Co-authors

Xavier VeraIntel Labs Barcelona, Malardalens University, Universitat Politecnica de Catalunya, UNSWVerified email at intel.com
Antonio GonzalezProfessor, Universitat Politecnica de CatalunyaVerified email at ac.upc.edu
Parthasarathy RanganathanGoogleVerified email at google.com
Adrian SampsonComputer Science, Cornell UniversityVerified email at cornell.edu
David PattersonProfessor of Computer Science, UC BerkeleyVerified email at cs.berkeley.edu
Rutwik JainPh.D. studentVerified email at wisc.edu
Shaan ShahUniversity of California San DiegoVerified email at ucsd.edu
Matthew D. SinclairUniversity of Wisconsin-Madison, AMD ResearchVerified email at cs.wisc.edu
Massimo PoncinoProfessor, Computing EngineeringVerified email at polito.it
Alberto MaciiPolitecnico di TorinoVerified email at polito.it
Enrico MaciiPolitecnico di TorinoVerified email at polito.it
Christina DelimitrouAssistant Professor, Massachusetts Institute of TechnologyVerified email at mit.edu
Sundar DevGoogleVerified email at google.com
Varun GohilMassachusetts Institute of TechnologyVerified email at mit.edu

Gaurang R. Upasani

Google

Verified email at google.com - Homepage

Computer Architecture


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery G Upasani, X Vera, A González Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on …, 2014	22	2014
Setting an error detection infrastructure with low cost acoustic wave detectors G Upasani, X Vera, A González Proceedings of the 39th International Symposium on Computer Architecture …, 2012	16	2012
A Case for Acoustic Wave Detectors for Soft-Errors G Upasani, X Vera, A Gonzalez IEEE, 2015	14	2015
Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery G Upasani, X Vera, A González On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, 85-91, 2013	10	2013
Framework for economical error recovery in embedded cores G Upasani, X Vera, A González On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International, 146-153, 2014	6	2014
Fifty years of ISCA: A data-driven retrospective on key trends G Upasani, MD Sinclair, A Sampson, P Ranganathan, D Patterson, ... arXiv preprint arXiv:2306.03964, 2023	4	2023
Soft error mitigation techniques for future chip multiprocessors GR Upasani Universitat Politècnica de Catalunya, 2016	3	2016
Reducing timing overhead in simultaneously clock-gated and power-gated designs by placement-aware clustering G Upasani, A Calimera, A Macii, E Macii, M Poncino Integrated Circuit and System Design. Power and Timing Modeling …, 2009	3	2009
The Importance of Generalizability in Machine Learning for Systems V Gohil, S Dev, G Upasani, D Lo, P Ranganathan, C Delimitrou IEEE Computer Architecture Letters, 2024		2024
Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective MD Sinclair, P Ranganathan, G Upasani, A Sampson, D Patterson, R Jain, ... IEEE Micro 43 (6), 109-124, 2023		2023
Development of Algorithms for the Integration of Clock-Gating and Power-Gating Techniques G Upasani, M Poncino, A Calimera		2009
Performance Evaluation of RAIDs O Kasilov, G Upasani		2008

The system can't perform the operation now. Try again later.

Articles 1–12

Citations per year

Duplicate citations

Merged citations

Add co-authorsCo-authors

Follow

Cited by

Co-authors