| Hardware support for WCET analysis of hard real-time multicore systems M Paolieri, E Quiñones, FJ Cazorla, G Bernat, M Valero ACM SIGARCH Computer Architecture News 37 (3), 57-68, 2009 | 296 | 2009 |
| Measurement-Based Probabilistic Timing Analysis for Multi-path Programs FJC Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio ... Proceedings of the 2012 24th Euromicro Conference on Real-Time Systems, 91-101, 2012 | 236* | 2012 |
| Dynamically controlled resource allocation in SMT processors FJ Cazorla, A Ramirez, M Valero, E Fernandez 37th International Symposium on Microarchitecture (MICRO-37'04), 171-182, 2004 | 207 | 2004 |
| Merasa: Multicore execution of hard real-time applications supporting analyzability T Ungerer, F Cazorla, P Sainrat, G Bernat, Z Petrov, C Rochange, ... IEEE Micro 30 (5), 66-75, 2010 | 181 | 2010 |
| Proartis: Probabilistically analyzable real-time systems FJ Cazorla, E Quiñones, T Vardanega, L Cucu, B Triquet, G Bernat, ... ACM Transactions on Embedded Computing Systems (TECS) 12 (2s), 1-26, 2013 | 171 | 2013 |
| An analyzable memory controller for hard real-time CMPs M Paolieri, E Quinones, FJ Cazorla, M Valero IEEE Embedded Systems Letters 1 (4), 86-90, 2009 | 168 | 2009 |
| Multicore resource management KJ Nesbit, M Moreto, FJ Cazorla, A Ramirez, M Valero, JE Smith IEEE micro 28 (3), 6-16, 2008 | 123 | 2008 |
| Predictable performance in SMT processors: Synergy between the OS and SMTs FJ Cazorla, PMW Knijnenburg, R Sakellariou, E Fernandez, A Ramirez, ... IEEE Transactions on Computers 55 (7), 785-799, 2006 | 105 | 2006 |
| A cache design for probabilistically analysable real-time systems L Kosmidis, J Abella, E Quiñones, FJ Cazorla 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 513-518, 2013 | 98 | 2013 |
| On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments P Radojković, S Girbal, A Grasset, E Quiñones, S Yehia, FJ Cazorla ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-25, 2012 | 84 | 2012 |
| Kilo-instruction processors: Overcoming the memory wall A Cristal, OJ Santana, F Cazorla, M Galluzzi, T Ramirez, M Pericas, ... IEEE micro 25 (3), 48-57, 2005 | 77 | 2005 |
| Predictable performance in SMT processors FJ Cazorla, PMW Knijnenburg, R Sakellariou, E Fernández, A Ramirez, ... Proceedings of the 1st Conference on Computing Frontiers, 433-443, 2004 | 76 | 2004 |
| Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study F Wartel, L Kosmidis, C Lo, B Triquet, E Quinones, J Abella, A Gogonel, ... 2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES …, 2013 | 73 | 2013 |
| QoS for high-performance SMT processors in embedded systems FJ Cazorla, A Ramirez, M Valero, PMW Knijnenburg, R Sakellariou, ... IEEE micro 24 (4), 24-31, 2004 | 70 | 2004 |
| WCET analysis methods: Pitfalls and challenges on their trustworthiness J Abella, C Hernandez, E Quiñones, FJ Cazorla, PR Conmy, ... 10th IEEE International Symposium on Industrial Embedded Systems (SIES), 1-10, 2015 | 68 | 2015 |
| A flexible heterogeneous multi-core architecture M Pericas, A Cristal, FJ Cazorla, R Gonzalez, DA Jimenez, M Valero 16th International Conference on Parallel Architecture and Compilation …, 2007 | 66 | 2007 |
| Upper-bounding program execution time with extreme value theory FJ Cazorla, T Vardanega, E Quiñones, J Abella 13th International Workshop on Worst-Case Execution Time Analysis, 2013 | 65 | 2013 |
| Adapting cache partitioning algorithms to pseudo-lru replacement policies K Kędzierski, M Moreto, FJ Cazorla, M Valero 2010 IEEE International Symposium on Parallel & Distributed Processing …, 2010 | 65 | 2010 |
| A dynamic scheduler for balancing HPC applications C Boneti, R Gioiosa, FJ Cazorla, M Valero SC'08: Proceedings of the 2008 ACM/IEEE conference on Supercomputing, 1-12, 2008 | 65 | 2008 |
| MLP-aware dynamic cache partitioning M Moreto, FJ Cazorla, A Ramirez, M Valero International Conference on High-Performance Embedded Architectures and …, 2008 | 65 | 2008 |
Jaume AbellaBarcelona Supercomputing Center (BSC)Verified email at bsc.es
