Dinesh Suresh
Title
Cited by
Cited by
Year
Profiling tools for hardware/software partitioning of embedded applications
DC Suresh, WA Najjar, F Vahid, JR Villarreal, G Stitt
ACM SIGPLAN Notices 38 (7), 189-198, 2003
942003
Improving software performance with configurable logic
J Villarreal, D Suresh, G Stitt, F Vahid, W Najjar
Design Automation for Embedded Systems 7 (4), 325-339, 2002
592002
Automatic compilation framework for bloom filter based intrusion detection
D Suresh, Z Guo, B Buyukkurt, W Najjar
Reconfigurable Computing: Architectures and Applications, 413-418, 2006
322006
Power efficient encoding techniques for off-chip data buses
DC Suresh, B Agrawal, J Yang, W Najjar, L Bhuyan
Proceedings of the 2003 international conference on Compilers, architecture …, 2003
232003
Tunable and energy efficient bus encoding techniques
DC Suresh, B Agrawal, J Yang, WA Najjar
Computers, IEEE Transactions on 58 (8), 1049-1062, 2009
192009
PROACTIVE LOOP FUSION OF NON-ADJACENT LOOPS WITH INTERVENING CONTROL FLOW INSTRUCTIONS
M Ye, D Suresh, D Ju, M Lai
US Patent App. 12/545,811, 2009
18*2009
A tunable bus encoder for off-chip data buses
DC Suresh, B Agrawal, J Yang, W Najjar
Proceedings of the 2005 international symposium on Low power electronics and …, 2005
172005
VALVE: variable length value encoder for off-chip data buses
DC Suresh, B Agrawal, W Najjar, J Yang
Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005
112005
Energy-efficient encoding techniques for off-chip data buses
DC Suresh, B Agrawal, J Yang, W Najjar
ACM Transactions on Embedded Computing Systems (TECS) 8 (2), 9, 2009
92009
Programmability and efficiency in reconfigurable computer systems
Z Guo, DC Suresh, WA Najjar
Workshop on Software Support for Reconfigurable Systems, held in conjunction …, 2003
82003
FV-MSB: A scheme for reducing transition activity on data buses
D Suresh, J Yang, C Zhang, B Agrawal, W Najjar
High Performance Computing-HiPC 2003, 44-54, 2003
82003
Loop level analysis of security and network applications
DC Suresh, SR Mohanty, WA Najjar, LN Bhuyan, F Vahid
Proceedings of the sixth Workshop on Computer Architecture Evaluation using …, 2003
72003
Power efficient instruction caches for embedded systems
D Suresh, W Najjar, J Yang
Embedded Computer Systems: Architectures, Modeling, and Simulation, 317-327, 2005
52005
Multi-core scalability-impacting compiler optimizations
DC Suresh, R Ju, M Lai, M Ye
Computer Science-Research and Development 25 (1), 15-24, 2010
2010
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Articles 1–14