Josep Torrellas - Google Scholar Citations

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Co-authors

Jose RenauProcessor of Computer Science Engineering, UCSCVerified email at ucsc.edu
Luis CezeProfessor of Computer Science and Engineering, University of WashingtonVerified email at cs.washington.edu
Smruti R. SarangiComputer Science, IIT DelhiVerified email at cse.iitd.ac.in
Milos PrvulovicProfessor of Computer Science, Georgia TechVerified email at cc.gatech.edu
Radu TeodorescuThe Ohio State UniversityVerified email at cse.ohio-state.edu
Michael HuangUniversity of RochesterVerified email at rochester.edu
Pablo MontesinosAppleVerified email at apple.com
Lawrence RauchwergerProfessor of Computer Science, University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Zheng ZhangProfessor of Computer Science and Engineering, NYU ShanghaiVerified email at nyu.edu
Wonsun AhnUniversity of PittsburghVerified email at cs.pitt.edu
Maria GarzaranResearch assistant professor, University of Illinois at Urbana-ChampaignVerified email at uiuc.edu
Yuanyuan ZhouUniversity of California, San DiegoVerified email at eng.ucsd.edu
John HennessyStanford UniversityVerified email at stanford.edu
Calin CascavalBarefoot NetworksVerified email at cascaval.us
Ulya R. KarpuzcuAssociate Professor of Electrical and Computer Engineering, University of Minnesota, Twin-CitiesVerified email at umn.edu
Nam Sung KimSamsung ElectronicsVerified email at illinois.edu
Pedro TrancosoDepartment of Computer Science and Engineering, Chalmers University of TechnologyVerified email at chalmers.se
Aditya AgrawalSenior Deep Learning Architect, NVIDIAVerified email at illinois.edu
Yan SolihinUniversity of Central FloridaVerified email at ucf.edu
Josep L. Larriba-PeyUniversitat Politècnica de CatalunyaVerified email at ac.upc.edu

Josep Torrellas

Professor of Computer Science, University of Illinois Urbana-Champaign

Verified email at illinois.edu - Homepage

Computer architecture parallel computing shared-memory architectures


Title	Cited by	Year
VARIUS: A model of process variation and resulting timing errors for microarchitects SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008	422	2008
A chip-multiprocessor architecture with speculative multithreading V Krishnan, J Torrellas IEEE Transactions on Computers 48 (9), 866-880, 1999	394	1999
Variation-aware application scheduling and power management for chip multiprocessors R Teodorescu, J Torrellas ACM SIGARCH computer architecture news 36 (3), 363-374, 2008	354	2008
Bulk disambiguation of speculative threads in multiprocessors L Ceze, J Tuck, J Torrellas, C Cascaval ACM SIGARCH Computer Architecture News 34 (2), 227-238, 2006	351	2006
ReVive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors M Prvulovic, Z Zhang, J Torrellas Proceedings 29th Annual International Symposium on Computer Architecture …, 2002	311	2002
False sharing and spatial locality in multiprocessor caches J Torrellas, HS Lam, JL Hennessy IEEE Transactions on Computers 43 (6), 651-663, 1994	282	1994
POSH: a TLS compiler that exploits program structure W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006	277	2006
Cherry: Checkpointed early resource recycling in out-of-order microprocessors J Martínez, J Renau, M Huang, M Prvulovic, J Torrellas Intl. Symp. on Microarchitecture (MICRO), 2002	272	2002
FlexRAM: Toward an advanced intelligent memory system Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999	265	1999
FlexRAM: Toward an advanced intelligent memory system Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas Computer Design (ICCD), 1999 IEEE International Conference on, 5-14, 1999	265	1999
Characterizing and predicting program behavior and its variability E Duesterwald, C Cascaval, S Dwarkadas 2003 12th International Conference on Parallel Architectures and Compilation …, 2003	264	2003
Architectural support for scalable speculative parallelization in shared-memory multiprocessors M Cintra, JF Martínez, J Torrellas ACM SIGARCH Computer Architecture News 28 (2), 13-24, 2000	264	2000
BulkSC: bulk enforcement of sequential consistency L Ceze, J Tuck, P Montesinos, J Torrellas ACM SIGARCH Computer Architecture News 35 (2), 278-289, 2007	261	2007
Speculative synchronization: applying thread-level speculation to explicitly parallel applications JF Martínez, J Torrellas ACM SIGOPS Operating Systems Review 36 (5), 18-29, 2002	248	2002
Proving program termination B Cook, A Podelski, A Rybalchenko Communications of the ACM 54 (5), 88-98, 2011	246*	2011
Facelift: Hiding and slowing down aging in multicores A Tiwari, J Torrellas Proceedings of the 41st annual IEEE/ACM International Symposium on …, 2008	245	2008
Delorean: Recording and deterministically replaying shared-memory multiprocessor execution ef? ciently P Montesinos, L Ceze, J Torrellas ACM SIGARCH Computer Architecture News 36 (3), 289-300, 2008	242	2008
Positional adaptation of processors: application to energy reduction MC Huang, J Renau, J Torrellas 30th Annual International Symposium on Computer Architecture, 2003 …, 2003	233	2003
A framework for dynamic energy efficiency and temperature management M Huang, J Renau, SM Yoo, J Torrellas Proceedings 33rd Annual IEEE/ACM International Symposium on …, 2000	204	2000
Volumetric preload measurement by thermodilution: a comparison with transoesophageal echocardiography CK Hofer, L Furrer, S Matter-Ensner, M Maloigne, R Klaghofer, M Genoni, ... British journal of anaesthesia 94 (6), 748-755, 2005	183	2005

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