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Marco Antonio Zanata Alves
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Using memory access traces to map threads and data on hierarchical multi-core platforms
EHM da Cruz, MAZ Alves, A Carissimi, POA Navaux, CP Ribeiro, ...
2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011
572011
Operand size reconfiguration for big data processing in memory
PC Santos, GF Oliveira, DG Tomé, MAZ Alves, EC Almeida, L Carro
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
472017
Sinuca: A validated micro-architecture simulator
MAZ Alves, C Villavieja, M Diener, FB Moreira, POA Navaux
2015 IEEE 17th International Conference on High Performance Computing and …, 2015
472015
Evaluating thread placement based on memory access patterns for multi-core processors
M Diener, F Madruga, E Rodrigues, M Alves, J Schneider, P Navaux, ...
2010 IEEE 12th International Conference on High Performance Computing and …, 2010
442010
Affinity-based thread and data mapping in shared memory systems
M Diener, EHM Cruz, MAZ Alves, POA Navaux, I Koren
ACM Computing Surveys (CSUR) 49 (4), 1-38, 2016
412016
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols
EHM Cruz, M Diener, MAZ Alves, POA Navaux
Journal of Parallel and Distributed Computing 74 (3), 2215-2228, 2014
322014
Large vector extensions inside the HMC
MAZ Alves, M Diener, PC Santos, L Carro
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
302016
Kernel-based thread and data mapping for improved memory affinity
M Diener, EHM Cruz, MAZ Alves, POA Navaux, A Busse, HU Heiss
IEEE Transactions on Parallel and Distributed Systems 27 (9), 2653-2666, 2015
292015
Process mapping based on memory access traces
EHM Cruz, MAZ Alves, POA Navaux
2010 11th Symposium on Computing Systems, 72-79, 2010
242010
Nim: An hmc-based machine for neuron computation
GF Oliveira, PC Santos, MAZ Alves, L Carro
International Symposium on Applied Reconfigurable Computing, 28-35, 2017
222017
Energy savings via dead sub-block prediction
MAZ Alves, K Khubaib, E Ebrahimi, VT Narasiman, C Villavieja, ...
Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE …, 2012
222012
Investigation of shared l2 cache on many-core processors
MAZ Alves, HC Freitas, POA Navaux
22th International Conference on Architecture of Computing Systems 2009, 1-10, 2009
202009
Impact of parallel workloads on NoC architecture design
HC de Freitas, LM Schnorr, MAZ Alves, POA Navaux
2010 18th euromicro conference on parallel, distributed and network-based …, 2010
192010
A compiler for automatic selection of suitable processing-in-memory instructions
H Ahmed, PC Santos, JPC Lima, RF Moura, MAZ Alves, ACS Beck, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 564-569, 2019
182019
Lapt: A locality-aware page table for thread and data mapping
EHM Cruz, M Diener, MAZ Alves, LL Pilla, POA Navaux
Parallel Computing 54, 59-71, 2016
172016
Increasing energy efficiency of processor caches via line usage predictors
MAZ Alves
172014
Locality and balance for communication-aware thread mapping in multicore systems
M Diener, EHM Cruz, MAZ Alves, MS Alhakeem, POA Navaux, HU Heiß
European Conference on Parallel Processing, 196-208, 2015
162015
Processing in 3D memories to speed up operations on complex data structures
PC Santos, GF Oliveira, JP Lima, MAZ Alves, L Carro, ACS Beck
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 897-900, 2018
152018
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
GF Oliveira, PC Santos, MAZ Alves, L Carro
2017 International Conference on Embedded Computer Systems: Architectures …, 2017
142017
Communication in shared memory: Concepts, definitions, and efficient detection
M Diener, EHM Cruz, MAZ Alves, POA Navaux
2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016
142016
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Articles 1–20