Marco Antonio Zanata Alves
TitleCited byYear
Using memory access traces to map threads and data on hierarchical multi-core platforms
EHM da Cruz, MAZ Alves, A Carissimi, POA Navaux, CP Ribeiro, ...
2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011
462011
Evaluating thread placement based on memory access patterns for multi-core processors
M Diener, F Madruga, E Rodrigues, M Alves, J Schneider, P Navaux, ...
2010 IEEE 12th International Conference on High Performance Computing and …, 2010
382010
Sinuca: A validated micro-architecture simulator
MAZ Alves, C Villavieja, M Diener, FB Moreira, POA Navaux
2015 IEEE 17th International Conference on High Performance Computing and …, 2015
322015
Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols
EHM Cruz, M Diener, MAZ Alves, POA Navaux
Journal of Parallel and Distributed Computing 74 (3), 2215-2228, 2014
272014
Affinity-based thread and data mapping in shared memory systems
M Diener, EHM Cruz, MAZ Alves, POA Navaux, I Koren
ACM Computing Surveys (CSUR) 49 (4), 64, 2017
252017
Operand size reconfiguration for big data processing in memory
PC Santos, GF Oliveira, DG Tomé, MAZ Alves, EC Almeida, L Carro
Proceedings of the Conference on Design, Automation & Test in Europe, 710-715, 2017
222017
Process mapping based on memory access traces
EHM Cruz, MAZ Alves, POA Navaux
2010 11th Symposium on Computing Systems, 72-79, 2010
212010
Large vector extensions inside the HMC
MAZ Alves, M Diener, PC Santos, L Carro
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016
202016
Energy savings via dead sub-block prediction
MAZ Alves, K Khubaib, E Ebrahimi, VT Narasiman, C Villavieja, ...
Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE …, 2012
172012
Investigation of shared l2 cache on many-core processors
MAZ Alves, HC Freitas, POA Navaux
22th International Conference on Architecture of Computing Systems 2009, 1-10, 2009
162009
Increasing energy efficiency of processor caches via line usage predictors
MAZ Alves
152014
Impact of parallel workloads on NoC architecture design
HC de Freitas, LM Schnorr, MAZ Alves, POA Navaux
2010 18th euromicro conference on parallel, distributed and network-based …, 2010
152010
Lapt: A locality-aware page table for thread and data mapping
EHM Cruz, M Diener, MAZ Alves, LL Pilla, POA Navaux
Parallel Computing 54, 59-71, 2016
122016
Optimizing memory locality using a locality-aware page table
EHM Cruz, M Diener, MAZ Alves, LL Pilla, POA Navaux
2014 IEEE 26th International Symposium on Computer Architecture and High …, 2014
112014
Kernel-based thread and data mapping for improved memory affinity
M Diener, EHM Cruz, MAZ Alves, POA Navaux, A Busse, HU Heiss
IEEE Transactions on Parallel and Distributed Systems 27 (9), 2653-2666, 2015
102015
Locality and balance for communication-aware thread mapping in multicore systems
M Diener, EHM Cruz, MAZ Alves, MS Alhakeem, POA Navaux, HU Heiß
European Conference on Parallel Processing, 196-208, 2015
102015
Eficiência energética em computação de alto desempenho: Uma abordagem em arquitetura e programação para green computing
SDK Mór, M Alves, JVF Lima, N Maillard, POA Navaux
XXXVII Seminário Integrado de Software e Hardware-SEMISH, 346-360, 2010
102010
Influência do compartilhamento de cache l2 em um chip multiprocessado sob cargas de trabalho com conjuntos de dados contíguos e não contíguos
MAZ Alves, HC Freitas, FR Wagner, POA Navaux
VIII Workshop em Sistemas Computacionais de Alto Desempenho, 27-34, 2007
102007
Exploring cache size and core count tradeoffs in systems with reduced memory access latency
PC Santos, MAZ Alves, M Diener, L Carro, POA Navaux
2016 24th Euromicro International Conference on Parallel, Distributed, and …, 2016
92016
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
GF Oliveira, PC Santos, MAZ Alves, L Carro
2017 International Conference on Embedded Computer Systems: Architectures …, 2017
82017
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Articles 1–20