| Modeling and detectability of full open gate defects in finfet technology F Forero, H Villacorta, M Renovell, V Champac IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (9 …, 2019 | 11 | 2019 |
| Impact of fin-height on SRAM soft error sensitivity and cell stability H Villacorta, J Segura, V Champac Journal of Electronic Testing 32, 307-314, 2016 | 11 | 2016 |
| Behavior and test of open-gate defects in FinFET based cells F Mesalles, H Villacorta, M Renovell, V Champac 2016 21th IEEE European Test Symposium (ETS), 1-6, 2016 | 9 | 2016 |
| Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test H Villacorta, V Champac, S Bota, J Segura Microelectronics Reliability 52 (11), 2799-2804, 2012 | 9 | 2012 |
| FinFET SRAM hardening through design and technology parameters considering process variations H Villacorta, V Champac, S Bota, J Segura 2013 14th European Conference on Radiation and Its Effects on Components and …, 2013 | 8 | 2013 |
| Impact of increasing the fin height on soft error rate and static noise margin in a finfet-based sram cell H Villacorta, R Gomez, S Bota, J Segura, V Champac 2015 16th Latin-American Test Symposium (LATS), 1-6, 2015 | 5 | 2015 |
| Analysis and detection of open-gate defects in redundant structures of a FinFET SRAM cell V Champac, J Mesalles, H Villacorta, F Vargas Journal of Electronic Testing 37 (3), 369-382, 2021 | 3 | 2021 |
| An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations Z Perez, H Villacorta, V Champac 2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018 | 3 | 2018 |
| Analysis of fin height on FinFET SRAM cell hardening H Villacorta, J Segura, S Bota, V Champac 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 3 | 2014 |
| Reliability analysis of small-delay defects due to via narrowing in signal paths H Villacorta, V Champac, R Gomez, C Hawkins, J Segura IEEE Design & Test 30 (6), 70-79, 2013 | 3 | 2013 |
| Reliability analysis of small delay defects in vias located in signal paths H Villacorta, V Champac, C Hawkins, J Segura 2010 11th Latin American Test Workshop, 1-6, 2010 | 3 | 2010 |
| Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations V Champac, H Villacorta, R Gomez-Fuentes, F Vargas, J Segura Journal of Electronic Testing, 1-12, 2024 | 1 | 2024 |
| Analysis and detection of hard-to-detect full open defects in FinFET based SRAM cells Z Perez, J Mesalles, H Villacorta, F Vargas, V Champac 2020 IEEE Latin-American Test Symposium (LATS), 1-6, 2020 | 1 | 2020 |
| Low VDD and body bias conditions for testing bridge defects in the presence of process variations H Villacorta, J Garcia-Gervacio, J Segura, V Champac Microelectronics Journal 46 (5), 398-403, 2015 | 1 | 2015 |
| Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias H Villacorta, J Garcia-Gervacio, V Champac, S Bota, J Martinez, J Segura 2013 14th Latin American Test Workshop-LATW, 1-6, 2013 | 1 | 2013 |
| Back-gate biasing of clock trees using a reference generator A Rousson, H Song, R Shivnaraine, C Holdenried, H Villacorta US Patent 11,705,903, 2023 | | 2023 |
| Shu-Mei Tseng Nektarios Tsoutsos Jaynarayan Tudu R. Ubar A Vali, M Mohammad, M Momtaz, N Na, K Namba, V Nelson, K Nepal, ... Journal of Electronic Testing 36, 5-6, 2020 | | 2020 |
| Skew violation verification in digital interconnect signals based on signal addition V Champac, H Villacorta, N Hernandez, J Figueras IEICE Electronics Express 11 (15), 20140201-20140201, 2014 | | 2014 |
| DISEÑO DE UN AMPLIFICADOR DE SEÑALES EEG CON UNA HERRAMIENTA DE DISEÑO AUTOMÁTICO BASADA EN EL MODELO BSIM3V3 HLV Minaya, JCS Pumarica | | |
| Diseño de un amplificador operacional de transconductancia para la adquisición de señales de electroencefalograma HL Villacorta Minaya Pontificia Universidad Católica del Perú, 0 | | |
Sebastia BotaAssociate Prof., Physics Dept., Universitat de les Illes BalearsVerified email at uib.es
