| FPGA/GPU-based acceleration for frequent itemsets mining: A comprehensive review L Bustio-Martínez, R Cumplido, M Letras, R Hernández-León, ... ACM Computing Surveys (CSUR) 54 (9), 1-35, 2021 | 22 | 2021 |
| Using hashing and lexicographic order for frequent itemsets mining on data streams L Bustio-Martínez, M Letras-Luna, R Cumplido, R Hernández-León, ... Journal of Parallel and Distributed Computing 125, 58-71, 2019 | 16 | 2019 |
| Model-based design automation of hardware/software co-designs for Xilinx Zynq PSoCs FJ Streit, M Letras, S Wildermann, B Hackenberg, J Falk, A Becher, ... 2018 international conference on ReConFigurable computing and FPGAs …, 2018 | 16 | 2018 |
| On the design of hardware architectures for parallel frequent itemsets mining M Letras, L Bustio-Martínez, R Cumplido, R Hernández-León, ... Expert Systems with Applications 157, 113440, 2020 | 9 | 2020 |
| Compilation of dataflow applications for multi-cores using adaptive multi-objective optimization T Schwarzer, J Falk, S Müller, M Letras, C Heidorn, S Wildermann, J Teich ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (3 …, 2019 | 9 | 2019 |
| Approximate frequent itemsets mining on data streams using hashing and lexicographie order in hardware L Bustio-Martínez, R Cumplido, M Letras-Luna, CF Uribe, ... 2017 IEEE 8th Latin American symposium on circuits & systems (LASCAS), 1-4, 2017 | 9 | 2017 |
| Multi-objective optimization of mapping dataflow applications to mpsocs using a hybrid evaluation combining analytic models and measurements M Letras, J Falk, T Schwarzer, J Teich ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (3 …, 2020 | 8 | 2020 |
| High-level synthesis for hardware/software co-design of distributed smart camera systems FJ Streit, M Letras, M Schid, J Falk, S Wildermann, J Teich Proceedings of the 11th international conference on distributed smart …, 2017 | 8 | 2017 |
| Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation C Pradhan, M Letras, J Teich arXiv preprint arXiv:2204.02443, 2022 | 6 | 2022 |
| Automatic conversion of simulink models to SysteMoC actor networks M Letras, J Falk, S Wildermann, J Teich Proceedings of the 20th International Workshop on Software and Compilers for …, 2017 | 6 | 2017 |
| A scalable and customizable processor array for implementing cellular genetic algorithms M Letras, A Morales-Reyes, R Cumplido Neurocomputing 175, 899-910, 2016 | 5 | 2016 |
| Decision tree-based throughput estimation to accelerate design space exploration for multi-core applications M Letras, J Falk, J Teich MBMV 2021; 24th Workshop, 1-11, 2021 | 4 | 2021 |
| Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers M Letras, J Falk, J Teich Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023 …, 2023 | 3 | 2023 |
| On the analytic evaluation of schedules via max-plus algebra for dse of multi-core architectures M Letras, J Falk, T Schwarzer, J Teich Proceedings of the 22nd International Workshop on Software and Compilers for …, 2019 | 3 | 2019 |
| Hardware architectures for frequent itemset mining based on equivalence classes partitioning M Letras, R Hernández-León, R Cumplido 2016 IEEE International Parallel and Distributed Processing Symposium …, 2016 | 3 | 2016 |
| A novel partition strategy for efficient implementation of 3d cellular genetic algorithms M Letras, A Morales-Reyes, R Cumplido, MG Martínez-Peñaloza, ... Microprocessors and Microsystems 104, 104986, 2024 | 2 | 2024 |
| Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems M Letras, J Falk, J Teich IEEE Access, 2024 | 1 | 2024 |
| An empirical analysis on dimensionality in cellular genetic algorithms A Morales-Reyes, HJ Escalante, M Letras, R Cumplido Proceedings of the 2015 Annual Conference on Genetic and Evolutionary …, 2015 | 1 | 2015 |
| Techniques for Efficient Performance Analysis and Memory Optimization in Mapping Dataflow Models of Computation Onto Embedded Systems MML Luna PQDT-Global, 2024 | | 2024 |
| Arquitectura Hardware en FPGA para el Minado de Conjuntos Frecuentes en Conjuntos de Datos Usando una Estrategia de Segmentacion MML Luna | | 2015 |
Jürgen TeichFull Professor, Computer Science, Friedrich-Alexander-Universität Erlangen-NürnbergDirección de correo verificada de cs.fau.de
